Enable the l2x0 outer cache controller
Web15 * You should have received a copy of the GNU General Public License http://visa.lab.asu.edu/gitlab/fstrace/android-kernel-msm-hammerhead-3.4-marshmallow-mr3/blob/382266ad5ad4119ec12df889afa5062a0a0cd6ae/arch/arm/mm/cache-l2x0.c
Enable the l2x0 outer cache controller
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WebBoards or SoCs which always require the cache controller: support to be present should select CACHE_L2X0 directly: instead of this option, thus preventing the user from: inadvertently configuring a broken kernel. config CACHE_L2X0: bool "Enable the L2x0 … WebHowever since the driver is widely used on other platforms I'd like to kindly ask any interested people for testing. Further three patches add implementation of .write_sec and …
WebAdd shutdown and restart functions to the L2X0 outer cache controller, so that machines which need to flush and disable the outer cache controller prior to executing the architecture reset or platform suspend code can do so. ... + cache_wait_always(l2x0_base + L2X0_CLEAN_INV_WAY, 0xff); + cache_sync(); ... http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff;h=ba9279519b371340e01cadf4c230e9d52a4bf8c4
WebAllow the L2X0 outer cache support to be configurable. author: Catalin Marinas Fri, 18 ... 21:43:17 +0000 (22:43 +0100) By default, this option was selected by the platform Kconfig. This patch adds "depends on" to L2X0 so that it can be enabled/disabled manually. Signed-off-by: Catalin Marinas … Web* For Aurora cache in no outer mode, enable via the CP15 coprocessor * broadcasting of cache commands to L2. ... controller is already configured, i.e. L2X0_CTRL_EN in L2X0_CTRL is set. Maybe I missed some check somewhere. Let me reread my code I wrote quite a long time ago and make sure.
Web* Enable the L2 cache controller. This function must only be * called when the cache controller is known to be disabled. */ static void l2c_enable(void __iomem *base, u32 …
Webouter_cache.set_debug = l2x0_set_debug; -printk(KERN_INFO "%s cache controller enabled\n", type); -printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, … rs3 gph priceWebJun 13, 2011 · the l2x0 was not reset. l2x0_disable cannot use writel, as writel calls wmb(), and wmb() may call outer_cache_sync, which takes the same spinlock as l2x0_disable. … rs3 gph street priceWebouter_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; +#endif printk(KERN_INFO "%s cache controller … rs3 grand exchange priceWebuClinux for Cortex-M3 and Cortex-M4, version 2.6.33 - linux-emcraft/cache-l2x0.c at master · EmcraftSystems/linux-emcraft rs3 grand exchange teleportWebSep 27, 2012 · Message ID: 1348738523-28609-2-git-send-email-gregory.clement@free-electrons.com (mailing list archive)State: New, archived: Headers: show rs3 grand libraryWeb- rewrote the code accessing l2x0_saved_regs from assembly code - added comment and reworked unconditional call to SMC_CMD_L2X0INVALL Patch summary: Tomasz Figa (7): ARM: l2c: Refactor the driver to use commit-like interface ARM: l2c: Add interface to ask hypervisor to configure L2C ARM: l2c: Get outer cache .write_sec callback from … rs3 grand exchange wikiWebMar 17, 2014 · Rather than decoding this from the ID register, store it in the l2c_init_data structure. This simplifies things some more, and allows us to better provide further details as to how we're driving the cache. We print the cache ID value anyway should we need to precisely identify the cache hardware. rs3 grand exchange update